A HIGH SPEED BINARY FLOATING POINT MULTIPLIER FOR ALL PRECISIONS
M. Malini Deepika, D. Jhansi · IJITR International Journal of Innovative Technology and Research - IJITR International Journal of Innovative Technology and Research · 2014
This paper presents upto double precision floating point multiplier [8,16,32,64] in verilog. In addition, the proposed designs are compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. A high speed floating point double precision multiplier is implemented on FPGA. The developed multiplier is implemented using Verilog HDL for the target FPGA Virtex-6. The designs are verified using Xilinx ISIM simulator.