Schedulability analysis of nMPRA processor based on multithreaded execution
Ionel Zagan, Vasile Gheorghiţă Găitan · 2016
This article presents several solutions meant to improve the performance of CPU architecture and it describes a fine-grained multithreading architecture empowered with a hardware scheduler that uses remapping techniques for the program counter, the register file and the pipeline registers. In this context, our main contribution relates to a custom CPU implementation in order to provide predictability execution for hard real-time tasks. Experimental data obtained during tests is analyzed in order to validate the proposed CPU, based on a fine-grained multithreading architecture and a fast switching operation between a blocked task and another one, scheduled by Hardware Scheduler Engine (nHSE). The resource differences between the original Multi Pipeline Register Architecture (nMPRA) implementation and the multithreading configuration are also taken in consideration.