Design and Implementation of the POWER5 TM Microprocessor
J. Clabes, Joshua Friedrich, Mark R. Sweet, J. DiLullo, Sam Chu, D. Plass, Paul L. Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, James D. Wagoner, Nicole Schwartz, Steve Runyon, G.M. Gorman, Phillip J. Restle, Ronald Kalla, Joseph McGill, Steve Dodson · 2004
offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in 130nm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz.