Expressing embedded systems verification aspects at higher abstraction level — SystemVerilog in Object Constraint Language (SVOCL)
Muhammad Harunur Rashid, Muhammad Waseem Anwar, Farooque Azam · 2016
In Model Based System Engineering (MBSE), structural and behavioral aspects of the system are modeled at higher abstraction level. However, verification aspects such as assertions based verification are generally treated at lower abstraction level, resulting in a reduced design productivity. This paper presents an approach to represent SystemVerilog assertions at higher abstraction level along with structural and behavioral aspects by proposing SVOCL (SystemVerilog in Object Constraint Language). The proposed OCL extension allows to represent verification aspects such that the minimum transformation efforts are required due to its close SystemVerilog semantics. Traffic light controller serves as a case study.