A circuit design of 32Kbyte integrated cache memory
Sakurai, Nogami, Sawada Sawada, Shirotori, Takayanagi, Iizuka, Maeda, Matsunaga, Fuji, Maegucm, Kobayasm, Andò, Hayakasfh, Mfyosfu, Sato · 1988
A cache memory is effective in enhancing CPU system throughput[1]. A circuit design aspect of a newly developed integrated cache memory which includes 32Kbyte DATA memory, with a typical IUT delay of 18ns is described. The present memory achieves four times larger DATA memory size together with much faster operation sped compared with the recently reported integrated cache memory[2l.