Evaluation of Architectural Support for Global Address-Based
Arvind Krishnamurthy, Klaus Erik Schauser, Chris J. Scheiman, David Culler, Katherine Yelick, Randolph Y. Wang · 1998
Large-scale parallel machines are incorporating increasingly sophisticated architectural support for user-level messaging and global memory access. We provide a systematic evaluation of a broad spectrum of current design alternatives based on our implementations of a global address language on the Thinking Machine CM-5, Intel Paragon, Meiko CS2, Cray T3D, and Berkeley NOW. This evaluation includes a range of compilation strategies that make varying use of the network processor; each is optimized for the target architecture and the particular strategy. We analyze a family of interacting issues that determine the performance tradeoffs in each implementation, quantify the resulting latency, overhead, and bandwidth of the global access operations, and demonstrate the effects on application performance.