A multirate root lpc speech synthesizer (linear prediction coding, analysis, synthesis, formant)
Chia-Chuan Hsiao · 1984
A root LPC (Linear Prediction coding) speech synthesizer with a variable bit rate has been built using a special purpose MOS-LSI circuit. The data rate can be from less than 1Kbps to greater than 10Kbps and any value in between. The output speech quality is determined by the desired input data rate. It can be used for speech storage and voice output systems which range from either large vocabulary (low bit rate and relatively low quality) or highly natural speech (high bit rate and less vocabulary). The root LPC speech synthesis is a combination of formant and LPC systems. The LPC polynomial is factored into quadratic factors. These factors are ordered by optimally matching their pole locations with overlapped regions in the Z-plane. The ordered factors are then used as the stages of a cascade form formant synthesizer. In the additional step for bit rate reduction each of these sections is treated independently. To lower the bit rate without losing the intelligibility, quadratic coefficient quantization based on a perceptual measurement and a section repeat algorithm based on dynamic programming are used. To upgrade the speech quality in terms of naturalness and smoothness, representative prediction residuals are used as the synthesis filter excitation for the voiced frames. By adjusting the maximal allowable spectral distances for section repeat and/or the reptition rate of the representative residuals, a continuum of bit rates with varying speech quality can be achieved. A chip was designed to implement this synthesizer, which has six quadratic stages in cascade. It uses a macrocell design approach and requires 16.2 square millimeters of die area. For 10kHz sampling rate it runs with a master clock of 3.4MHz.