Circuit Design Techniques for a Floating-Point Processor
Timothy H Hu · UC Berkeley · 1987
This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit. Three most interesting circuit blocks are discussed which include a fast adder, a leading one detector and a shifter. Mixed logic with static and dynamic circuits are used. The chip is implemented in a 1.6 micron, N-well, double-metal CMOS process (HP CMOS40). The timing and area of the above three modules are as follows: 66 bit adder * Delay - Crystal 36 ns, SPICE 33 ns * Size - 4757 x 553 lambda, which is 3806 x 442 um. 67 bit Leading one detector * Delay - Crystal 20.5 ns, SPICE 18 ns * Size - 4901 x 463 lambda, which is 3920 x 320 um. 67 bit shifter with Sticky Logic * Delay - Shifting 15 ns, Sticky bit (latched into output latch) 25 ns * Size - The whole module with decoder is 5359 x 1414 lambda, which is 4287 x 1131 um