Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table
Mohammadreza Soltaniyeh, I. Kadayif, Özcan Öztürk · 2016
Chip multiprocessors (CMPs) require effective cache coherence protocols as well as fast virtual-to-physical address translation mechanisms for high performance. Directory-based cache coherence protocols are the state-of-the-art approaches in many-core CMPs to keep the data blocks coherent at the last level private caches. However, the area overhead and high associativity requirement of the directory structures may not scale well with increasingly higher number of cores.