Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors
Ajaykumar Kannan, Natalie Enright Jerger, Gabriel H. Loh · IEEE Micro · 2016
Silicon interposers enable the integration of multiple stacks of in-package memory to provide higher bandwidth or lower energy for memory accesses. Once the interposer has been paid for, there are new opportunities to exploit the interposer. In this article, the authors exploit the interposer to "disintegrate" a multicore CPU chip into smaller chips that collectively cost less to manufacture than a single large chip. They study the performance-cost tradeoffs of interposer-based, multichip, multicore systems and propose new interposer network-on-chip (NoC) organizations to mitigate the performance challenges while preserving the cost benefits. Although this article focuses on NoC support for disintegrated systems, it paves the way for a range of new research problems in interposer-based disintegrated systems.