An efficient mapping algorithm on 2-D mesh Network-on-Chip with reconfigurable switches
Salih Bayar, Arda Yurdakul · 2016
As Network-on-Chips (NoC) are the most scalable architecture with growing number of processing elements in multi-core systems, communication data between nodes tend to travel through more routers. Hence, a good mapping algorithm must be designed in order to locate most communicating nodes neighbour to each other. However, this may not be sufficient for data-intensive applications such as audio, video, telecommunication and etc. In such multi-core applications, processing elements communicate to each other with heavy load statically in most cases. Passing heavy load data through routers might make the routers bottleneck of the system. In this paper, we propose a custom 2-D NoC architecture with simple reconfigurable switches, which can be configured during both design and runtime according to the application requirements. We designed a mapping algorithm which tries to set paths through these simple switches instead of complicated routers all the way. Experimental results show that our mapping algorithm reduces routing cost up to by 79.96% for real life embedded applications.