Coded Network Switches for Improved Throughput
Rami Cohen, Yuval Cassuto · 2016
With the increasing demand for network bandwidth, network switches face the challenge of serving growing data rates. To parallelize the process of writing and reading packets to the switch memory, multiple memory units (MUs) are deployed in parallel in the switch fabric. However, memory contention may occur if packets requested to read happen to share one or more MUs, due to memory bandwidth limitations. Avoiding such contention in the write stage is limited as the reading schedule of packets is not known upon arrival of the packets to the switch. Thus, efficient packet placement and read policies are required.