Synthesis for testability using test functions
Suman Kanjilal · 1994
We develop new methods to synthesize very large digital circuits with testability. For a given sequential function, called the object function, we define a test function with the same number of states as the given function. The test function has predetermined synchronizing and distinguishing sequences. We merge the test function in the state diagram of the object function prior to its synthesis. The key idea is to embed the test function without increasing the state variable dependencies of the object function. Experiments with MCNC synthesis benchmarks have produced implementations having significantly lower test logic overhead than the popular design for testability method of scan. The test generation for our implementation is combinational and has the same complexity as the scan method. To apply the test function method to large gate-level designs, we propose a new series-connected finite state machine test architecture. The main idea is to match the output symbols of one test machine with the input symbols of the next test machine in the series. We partition the circuit into interconnected finite state machine components. A test machine is embedded into each component which is then resynthesized. Again, the entire circuit is easily tested. The method is applied to ISCAS '89 benchmark circuits using a testability-directed partitioning procedure. The overhead required is lower than scan. We also report the discovery of a little known condition occurring in circuits synthesized with embedded test functions. We show that a fault can result in partial or total loss of the test function. Test complexity prohibits a complete verification of the test function and as a result, the tests, generated assuming full integrity of the test function, can become invalid. We devise a method of synthesizing finite state machines with fault tolerant test machines. This is accomplished by a constrained logic minimization procedure. The machine is synthesized as a programmable logic array and the testing of the test machine is altogether eliminated. Testing of the object function again requires only combinational test generation. The concept of a fault tolerant test function is applicable to single machines, as well as to large partitioned circuits.