Axon: Host-Network Interface Design
James P. G. Sterbenz · Open Scholarship Institutional Repository (Washington University in St. Louis) · 1990
This paper describes the Axon host-network interface architecture. The Axon project is investigating an integrated design of host architecture, operating systems, and communications protocols to allow applications to utilize the high bandwidth provided by the next generation of communications networks. The Axon host architecture and network interface is designed to provide a high bandwidth low latency path directly between the network and host memory. A pipelined communications processor (CMP) serves as a network interface with direct access to host memory, capable of delivering bandwidth in excess of 1 Gbps to applications. This provides the ability to support demanding applications such as scientific visualizations and imaging, requiring high bandwidth and low latency.