An Efficient VLSI Architecture of a Reconfigurable Pulse- Shaping FIR Interpolation Filter for Multi standard DUC
M. Ramana Reddy · 2015
Most of the area occupied in the design of FIR filter is the multiplier. The low power and area architecture of pulse shaping FIR filter for digital up converter was designed. In the existing system, the two bit binary common sub-expression based binary common sub-expression elimination algorithm and shift and add method was used to generate the partial products. In this paper, carry save adder is used instead of shift and add method and also the simple arithmetic adders of multiplexer unit is replaced by carry save adder. The number of additions and multiplications are reduced using this technique. The designed pulse shaping FIR filter is synthesized and simulated using Xilinx ISE 14.3.