Parallel algorithm that considers energy efficiency and time efficiency
Toshihiro Yoshizumi, Takaaki Goto, Yoshinao Isobe, Kazuhito Ohmaki, Hideki Mori, Kensei Tsuchida · 2016
An embedded system often consists of two or more processors for efficient control of various devices in parallel. However, it is difficult to correctly design parallel software for such an embedded system because of unexpected interference among processors. It is using a formal method for the development of that system. Further more, power saving called Green IT is also an important issue in high performance computing. In this paper, we present an algorithm for parallel computing based on CSP, which is a theory for communicating processes, and report the performance evaluation results of the algorithm on XMOS, which is an event-driven multi-core processor. We show that power consumption can be reduced by event-driven style communications, and presents a improved parallel sorting model.