Design guidelines for embeded NoCs on FPGAs
Noha Gamal, Hossam A. H. Fahmy, Yehea Ismail, Hassan Mostafa · 2016
Including Networks-on-Chip (NoCs) within FPGAs has become necessary to overcome the problems of point-to-point interconnect scheme. This will enable interfacing with high speed IOs and partial dynamic reconfiguration (PDR), reduce the compile time and improve the system performance. We compared FPGA-specific NoC components on soft and hard implementations and analyzed the efficiency gap between the two technologies to get design constraints in this space. Input module that includes memory buffers, implemented using block RAMs (BRAMs), is the module with the smallest gaps: 1.8x area, 2.9x delay and 5.3x power. Switch has the largest gap: 90x area, 7x delay and 53x power. If the router is totally hard implemented, this will save 9x area, 3.7x delay and 12x power at the expense of no flexibility (reconfigurability). By comparing our results with same flow on ASIC-specific router, we show that using FPGA-specific NoCs design improves the utility by a factor of 3x in area with a slight increase in the delay.