Process Algebraic Approach to Timing Analysis of Superscalar Processor Programs
Hee-Jun Yoo, Ki-Huen Lee, Jin‐Young Choi · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2000
Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.