Design and Analysis of a Digit-Serial $AB^{2}$ Systolic Arrays in $GF(2^{m})$
Nam-Yeun Kim, Yoo Kee-Young · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2005
Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over and it is computed by performing the repetitive multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the operation in GF. To obtain L×L digit-serial-in-serial-out architecture, new algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about , the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial systolic architecture is approximately lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.