An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology
Gi-Hak Sim, O Ik-Gyun, Sangmin hong, Beom-Seon Yu, Gi-Yeong Lee, Tae-Won Jo · Journal of the Institute of Electronics Engineers of Korea · 2000
An 88+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.