The Hardware Architecture of Efficient Intra Predictor for H.264/AVC Decoder
Ok Kim, Ryoo Kwangki · Journal of the Institute of Electronics Engineers of Korea · 2010
In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of . As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.