Synthesis of Asynchronous Circuits from Deterministic Signal Transition Graph with Timing Constraints
Hee‐Sook Kim, Sung-Tae Jung · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2000
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic signal transition graph specification with timing constraints. First, a timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding paths in the graph. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates circuits that have nearly the same area as compared to previous methods.