Efficient systolic VLSI architecture for division in $GF(2^m)$
Kim Ju-Young, Tae-geun Park · Journal of the Institute of Electronics Engineers of Korea · 2007
The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis finite-field divider using Dongbuanam standard cell library and the maximum clock frequency is 400MHz.