A Fast and Scalable Priority Queue Hardware Architecture for Packet Schedulers
Sang‐Gyun Kim, Byungin Moon · Journal of the Institute of Electronics Engineers of Korea · 2007
This paper proposes a fast and scalable priority queue architecture for use in high-speed networks which supports quality of service (QoS) guarantees. This architecture is cost-effective since a single queue can generate outputs to multiple out-links. Also, compared with the previous multiple systolic array priority queues, the proposed queue provides fast output generation which is important to high-speed packet schedulers, using a special control block. In addition this architecture provides the feature of high scalability.