Fast and Accurate Performance Estimation of Bus Matrix for Multi-Processor System-on-Chip (MPSoC)
Sungchan Kim, Soonhoi Ha · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2008
This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ( times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.