SoC for car navigation systems with a 53.3 GOPS image recognition engine
Hideaki Kido, Shoji Muramatsu, Yasuhiko Hoshi, Hiroyuki Hamasaki, Atsuhi Nakamura, Akihiro Yamamoto · 2009
SH-Navi3 embeds : High performance dual RISC processors (1920 MIPS) : 2D/3D graphic accelerators : Image recognition engine - High-speed processing (up to 53.3GOPS): parallel processing + pipeline architecture + function specific accelerator - Bus traffic reduction & Line programmability: PIPE architecture.