Practical Issues in Clock Network Design
Chris Chong-Nuen Chu, Min Pan · Auerbach Publications eBooks · 2008
This chapter presents the clock network designs of several high-performance microprocessors to illustrate how the basic techniques. It focuses on the clock network design of high-performance microprocessors as the stringent slew requirements make the design most challenging. For synthesized macros that had many latches, and therefore multiple clock blocks, a clock optimization tool was used that reassigned latches to clock blocks based on cell placement. The microprocessor uses a single chip-wide clock domain, with no active or programmable skew-reduction circuitry. The clock network consists of a pre-global clock network, a global clock grid, and local clocking. The fuse-based deskew can remove unintentional clock skew caused by on-die process variations and clock network design mismatches. A phase detector residing within the local controller of the deskew buffer analyzes the phase difference between the reference clock and a local feedback clock sampled from the regional clock grid.