Assertion based verification of transaction level models
Bernhard Niemann, Christian D. Haubelt, Integrierte Schaltungen Hardware-software-co-design · 2006
Abstract. Transaction Level Modeling with SystemC has become a de-facto industry standard for modeling of system-on-chip designs. The correctness of these models is therefore of crucial importance. In this paper, we propose a novel methodology to apply Assertion-Based Verification to Transaction Level Models. The novelty is based on two contributions: (1) Using Aspect-Oriented Programming techniques permits transaction recording without having to modify the existing TLM. (2) Mapping of transactions to Boolean signals and automatic event clock creation enables the concise formulation of assertions. In contrast to other approaches, our methodology allows direct Assertion-Based Verification of the TLM without the necessity of an additional abstract model. 1 Introduction and Related Work In this paper, we propose a methodology to use assertions for the verification of Transaction Level Models (TLMs). Specifically, we show how to use SystemVerilog Assertions [1] for the functional verification of a SystemC [2] TLM. Instead of treating a transaction as a complex data structure, we associate with each transaction a Boolean signal which is true during the