Performance Evaluation of an On-Chip Multiprocessor for Object Recognition
Yongwha Chung, Kyoung Park, Sunghoon Choi, Woo-Jong Hahn · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2000
Object recognition is a challenging application for high-performance computing. Currently, the superscalar architecture dominates todays microprocessor marketplace. As more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the object recognition on the on-chip multiprocessor, which will be employed in general-purpose parallel machines. To obtain the performance characteristics of the microprocessor, a program-driven simulator and its programming environment were developed. The simulation results showed that the on-chip multiprocessor can exploit thread level parallelisms effectively and offer a promising architecture for the object recognition application.