LAPG-2: A Cost-Efficient Design Verification Platform with Virtual Logic Analyzer and Pattern Generator
Soo-Yun Hwang, Dong-Soo Kang, Kyoungson Jhang, Yi Kang · Jeongbo gwahaghoe nonmunji. si'seu'tem mich i'lon · 2008
This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.