Short burst software transparent on-line MBIST
Alan Becker · 2016
A new methodology and algorithm is presented for testing on-chip memories concurrently with the normal operation of a processor, which has little or no effect on its performance. The test algorithm uses a series of short burst of memory access and does not destroy the memory contents. This paper describes the implementation of the memory built-in self-test (MBIST) methodology in the ARM® Cortex®-M7 microprocessor to allow on-line testing of the Level 1 cache SRAMs and Tightly Coupled Memories (TCMs). A programmable MBIST controller is also described that can execute the algorithm to test memories at-speed and autonomously from software running on a processor, via the ARM standard MBIST interface.