A Truncated Booth Multiplier Architecture for Low Power Design
Kwang-Hyun Lee, Chong-Suck Park · Journal of the Institute of Electronics Engineers of Korea · 2000
In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP applications, all of multiplier products were not used, but only upper bits of product were used. Kidambi proposed truncated unsigned multiplier for this idea. in this paper, we adopt this scheme to Booth multiplier which can be used real DSP systems. Also, zero input guarantees zero output that was not provided in previous paper. In addition, we propose bit extension scheme to reduce truncation error more and more. And, we adopted this multiplier to FIR filters for more efficient design.