Hierarchical TLB Representation and Memory Management Schemes for Reducing Memory Access Overhead
Changwoo Min, Tae-Hyoung Kim, Young-Ik Eom · 2012
In advances of computing hardware, size of physical memory per machine is getting larger. Moreover, the working set size per application is also getting larger, as virtualization and server consolidation is getting popular. However, the relative coverage of Translation Look-aside Buffer (TLB), which caches mappings between virtual address and physical address, is getting smaller as size of physical memory increases. Thus, TLB miss becomes more frequent and the cost of memory access is getting higher. To address this problem, we propose a new TLB mechanism that represents multiple mappings using one TLB entry and several operating system schemes to facilitate the effectiveness of the proposed TLB mechanism. Our simulation results show the proposed mechanism is effective to reduce TLB miss on real world workload.