Design and Implementation of Reconfigurable ECC Arithmetic Unit in GF(2~m)
Тао Чен · Jisuanji gongcheng · 2008
A finite field polynomial arithmetic unit architecture is proposed in this paper for reconfigurable ECC. The multiplier based on previousdigit-serial multiplier architecture uses bit-parallel architecture of local parallel to eliminate reduction modulo circuit effectively, and the multiplierarchitecture is the same with arbitrary irreducible polynomials. The squaring architecture computes squares by using an LSB, or an LSD multiplierwith an adder. Data format of import is controlled through data interface, which achieves requirements of point multiplication for different finitefields.