Diagnosis of Delay Faults in the Presence of Clock Delays Considering Hazards
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shinya Kobayashi, Kewal K. Saluja · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2015
Presence of hazards can often lead to poor diagnosis. In this paper we propose a diagnosis method for gate delay faults in the presence of clock delays and hazards. Candidate faults are deduced using a fault dictionary which is created by the fault simulation considering hazard signals. Our diagnosis method can deduce candidate faults successfully even when a fault is activated by a hazard signal or when hazard signals are propagated to outputs, though conventional methods without considering hazards often fail to do so.