Implementation of Square Root Arithmetic Based on FPGA
JI Xiaoliang · Modern Electronics Technique · 2007
Square root arithmetic is one of the basic arithmetic,but it is hard to implement on FPGA because of the complexity.Usually,the non-restoring square root algorithm is low-cost iterative implementation which uses a traditional adder/subtrator.While making better use of the resource,the speed is much slower.In this paper,we present a fast square root based on FPGAs,it is high-throughput pipelined implementation which uses multiple adder/subtractors.