The Design and Implementation of Sequential Circuits in FPGA Configurable Logic Block
Jiarong Tong · Dianzi xuebao · 2008
This paper presented the design and implementation of two sequential circuits in FPGA configurable logic block,namely,distributed RAM and shift register.In order to decrease the rigorous demand of the timing controller,static latche is used to implement synchronous writing of distributed RAM.In order to eliminate the effect of charge sharing,the isolation is used to separate the passageway between ramcells.As an example of the CLB composed of two four inputs LUTs,the design and implementation method of the above sequential function is presented.It is concluded that the proposed method has its advantage in timing controller,charge sharing and die area.