Data Collecting Algorithm for Reverse Analysis of Synchronous Logic PLD
Zeng Guangyu · Jisuanji gongcheng · 2008
The key problem in the reverse analysis of encrypted Programmable Logic Devices(PLD) using logic analysis techniques is to collect effective and self-contained data set,especially for timing PLD.An efficient data collecting algorithm is presented whichs suit for large scale and multi-state synchronous PLDs.The algorithm builds non-complete state graph and finds the shortest path for state migration form initial state to each effect state.The algorithm has ideal time and space cost and has been used in the PLD reverse engineering system.