Test Vectors Generating Method Based on Internal Functional Modules for RTL
Xu Rui · Jisuanji gongcheng · 2011
In order to reduce hardware overhead,this paper proposes a method where the adders,subtracters and multipliers inside of a data path are used to generate test vectors.Experimental results show that the proposed Design For Testability(DFT) and test scheduling approach has good performance and practicality.Under a given power constraint,the hardware overhead can be reduced from 10.7% to 73.4%.The test application time can also be reduced up to 22.4%.