DECREASE OF HARDWARE AMOUNT IN LOGIC CIRCUIT OF MOORE FSM
Uniwersytet Zielonogórski, Alexander A. Barkalov · 2008
Method of decrease in the number of PAL macrocells in logic circuit of Moore FSM is proposed. The method is based on simultaneous application of refined state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. The results of experiments are shown.