The design of a multiplier-adder unit in the high-speed FIR filter
Honghui Deng · Electronic Instrumentation Customers · 2008
This paper implements a kind of high-speed constant multiplier-adder unit, which is based on shift-add operation. This multiplier-adder unit is based on CSD coding and adopts both 3-2 compressor and Wallace tree, its multiply-add operation is realized by entire parallel approach, and Three-Greedy connection algorithm is applied to this unit to improve its speed. As a result, this new multiplier-adder unit has a significant speed advantage compared with the traditional direct structure. Moreover, it occupied smaller area than parallel multiplier-adder unit which is applied in general multiplier. This unit has been applied in a interpolation filter of a high-speed DAC chip.