Fine-Grained Parallel K-means Clustering Algorithm on FPGA
Zhao Jian-Xun · Computer Engineering and Science · 2009
We propose a systolic array structure including one master PE and multiple slave PEs for fine grain hardware implementation on FPGA.We partition tasks by rows and assign tasks to PEs for load balance.We exploit data reuse schemes to reduce the need to load data from external memory.To our knowledge,our implementation with 4 PEs is the only FPGA accelerator(XC5VLX330) implementing the complete K-means clustering algorithm.The experimental results show a factor of more than 15 speedup over the Cluster 3.0 software running on a PC platform with Pentium 4 2.66GHz CPU.