Riverside Optimizing Compiler for Configurable Computing Parallel Program Compilation Method
Wei Zhang · Tance yu kongzhi xuebao · 2011
To improve the efficiency and reduce the difficulty of FPGA-based parallel computing,parallel algorithm using high-level language programming was proposed,which combined with ROCCC compiler to convert the code for hardware acceleration.ROCCC based parallel computing flow of FPGA was put forward,and took matrix multiplication as an example to testify feasibility of it.The simulation results indicated that the methed was of high feasibility,and it could reduce the development circle and programming difficulty.