Design and implementation of a 1.2 GSPS digital channelized receiver
Zhang Er-yang · Systems engineering and electronics · 2009
Based on the efficient structure of the real signal digital channelized receiver,a 1.2 GSPS receiver of 16 sub-channels is realized in hardware platform.In FPGA design,reliable receiving of high speed data as well as the processing speed and resource optimizing inside the chip are maturely considered to insure the good performance.The intermediate frequency test results of the receiver verify its correctness and stability.