Static Error Detection Method for RTL Design Verification
Duan Yonghao · Jisuanji gongcheng · 2011
For detecting the potential common errors of integrated circuit designs quickly and efficiently,this paper introduces a novel error defection approach based on static analysis.The proposed approach can find errors,such as deadlocks in state machines,errors in pin configuration, by automatically deriving information about the behavior of Register-Transfer Level(RTL) design under verification.Experimental results show that compared with other verification methods,the static method can find errors automatically,efficiently and accurately.It can be reused for any other RTL design to detect errors before simulation.