Low power optimization for MPRM circuits based on dynamic logic
Hui Li, Pengjun Wang · Journal of Circuits and Systems · 2010
For an n-veriable logic function, power and area of 3n Mixed-Polarity Reed-Muller (MPRM) circuit implementations are different. Power and area estimation model of MPRM circuits are established by analyze of power consumptions of CMOS circuits and low power decompositions for MPRM circuits in dynamic logic. Then a fast algorithm of low power decomposition of dynamic logic-base MPRM circuits is proposed. Based on estimation models and decomposition algorithm, and combining tabular conversion techniques, exhaustive search algorithm is applied in low power optimization for mid-small scale MPRM circuits and genetic algorithm for large scale accordingly. Through several MCNC and ISCAS Benchmark tests, the results show that compared to Boolean circuits and Fixed-Polarity Reed-Muller (FPRM) circuits, mid-small scale MPRM circuits have achieved save power and area up to 80.65% and 50.98% on average, large scale MPRM circuits up to 80.65% and 50.98% on average, respectively.