High Effective Dynamic Reconfigurable Registers in FPGA
Jiarong Tong · Fudan xuebao. Ziran Kexue ban · 2009
A new type of configurable register circuit in FPGA is proposed.Without wasting combinational logic resources in FPGA,the circuit can be independently configured as 56 types of latches and D Flip-Flops.At the cost of 50% area,the proposed register reduces 70% delay and 90% area of the whole circuit when configured as a complicated sequential circuit.Meanwhile,in order to improve the slow speed in dynamic configuration for the Xilinx Virtex series,the capture and writeback circuits are also included in the proposed circuit,which helps to realize the status saving and resuming of the circuits during dynamic reconfiguration and to accelerate the reconfiguration speed for FPGA.