IP Design of Fast Multiplier-accumulator
Qinshu Chen · Journal of Hunan Institute of Engineering · 2004
A new method is introduced by designing IP cores of 8bit fast multiplier-accumulator.The capacity of the multiplier-accumulator is boosted when some techniques are used in the module of the Wallace's tree.Its structure is expressed in VerilogHDL and implemented in the xc2vp20 produced by Xilinx Inc.The result shows a 19.8% decrease in the FPGA sources and a 9.5% increase in the performance with this new method.