Implementation of Optimal FIR Filter Based on FPGA
Cheng Shu-ying · Modern Electronics Technique · 2011
The traditional FIR digital filter was modified with the concept of increasing the speed and reducing the area.Taking into account of the characteristics of FPGA,the Booth Radix-2 algorithm multiplier and the fast adder were designed in the combination with CSA adder and a tree structure,and then the adder and multiplier were used successfully in the design of FIR digital filter.The coefficients of the filter were generated by Matlab.Simulation and synthesis results show that Booth algorithm multiplier and adder tree based on CSA algorithm not only meet the performance requirements of FIR digital filter but also optimize the area on the circuit and especially the speed,and the optimization is more evident when there are a large amount of data.