Design and performance analysis of non-inclusive cache on CMP
WU Cheng-yong · Jisuanji gongcheng yu sheji · 2008
As semiconductor technology develops,it is possible to pack billions of transistors on a single die.How to utilize such a large resources budget efficiently has been on-going for years.There is clear evidence of the trend that more and more commercial offe-rings and research projects address chip multiprocessors(CMP) design.Many design options on how to organize cache hierarchy before hitting memory wall to raise the performance of CMP architecture are presented and non-inclusive cache is one of those.After evaluating several different organizations of cache hierarchy on CMP with partial Splash2 benchmarks,the result shows that non-inclusive cache can get benefits of 8.3% improvement in average data access time from reducing off-chip access.As non-inclusive cache can also save on-chip resources,it is proposed to improve CMP's performance by organizing the last line of defense of cache hierarchy with non-in-clusive cache before going off-chip.